Notice and Invitation
Oral Defense of Doctoral Dissertation
The Volgenau School of Engineering, George Mason University
Hadi Mardani Kamali
Bachelor of Science, K. N. Toosi University of Technology, 2011
Master of Science, Sharif University of Technology, 2013
The Evolution of Logic Locking: Towards Next Generation Logic Locking Countermeasures
Thursday, June 3, 2021, 10:30 AM 12:30 PM
Zoom Meeting Link: https://gmu.zoom.us/j/97804867550
All are invited to attend.
Dr. Avesta Sasan, Chair
Dr. Kris Gaj
Dr. Brian Mark
Dr. Fei Li
Logic obfuscation, a.k.a. logic locking, is a proactive Design-for-Trust (DfTr) technique that aims to address the important security concerns in the IC supply chain and combats the existing
security threats and trust challenges. Logic locking is the ability to add limited post-manufacturing programmability into the IC to conceal the ICs functionality from the source of vulnerabilities, such as untrusted stakeholders. However, over the years,
the reliability and trustworthiness of logic locking have been seriously challenged by different de-obfuscation attacks.
In this dissertation, after elaborating the current state of logic locking in the literature, we aim to open a new direction as a means of logic locking that provides much higher robustness.
Unlike almost all previous logic locking solutions that rely on XOR-based locking focusing on the logic functions, we will investigate and evaluate MUX-based logic locking techniques that add ambiguity to the routing of the wires within an IC. We will introduce
two routing-based (MUX-based) logic locking techniques, and with a comprehensive comparison with the state-of-the-art logic locking techniques, we will evaluate them in terms of security (resiliency against the attacks), as well as the implementation effort
and overhead. Relying on these new MUX-based logic locking techniques, we will go one step further and engage such structures for locking the Design-for-Testability (DFT) structures, known as scan chain architecture. We demonstrate how MUX-based (routing)
logic locking integrated with in-memory computation could boost the robustness of the IC against state-of-the-art attacks at much lower overhead. We also investigate the efficiency of DFT blockage techniques compared to the locking techniques, and by introducing
a new blockage mechanism, we show how such solutions could provide resiliency at lower overhead