Notice and Invitation
Oral Defense of Doctoral Dissertation The Volgenau School of Engineering, George Mason University
Master of Science, University of Bridgeport, 2015
Golden-Chip Free Side Channel Delay Analysis Test for Hardware Trojan and Recycled IC Detection
Friday, April 23rd, 2021, 1:00 PM
Zoom Meeting Link: https://gmu.zoom.us/j/91965871162
All are invited to attend.
Dr. Avesta Sasan, Chair
Dr. Khaled Khasawneh
Dr. Jim Jones
Dr. Behzad Esmaeili
The distributed manufacturing supply chain of Integrated Circuits (IC) introduces many vulnerabilities during IC's life cycle. An adversary in an untrusted foundry can exploit these weaknesses
to design malicious hardware attacks that target the integrity, reliability, and trustworthiness of fabricated ICs.
This work introduces a set of physical-aware and learning assisted modeling techniques, followed by test methodologies, for Hardware security in the post-fabrication stage. The proposed detection
approach targets to identify Hardware-Trojan infected chips and recycled-ICs. Unlike the prior art, this flow does not require a Golden fabricated chip as a fingerprint to compare the side-channel signals. Instead, by modeling the voltage drop and voltage
noise pre-fabrication and training a Neural Network post-fabrication, our proposed technique can improve the timing model collected during timing closure and produces a Neural Assisted Golden Timing Model (NGTM) for side-channel delay-signal analysis.
The Neural Network acts as a process tracking watchdog for correlating the static timing data (produced at design time) to the delay information obtained from a clock frequency sweeping test.
Proposed detection flow enables Hardware Trojan detection close to 90%, and 100% recycled-IC detection in the simulated scenarios.