Dear Students,

Here's another approved seminar for ECE 795:

ECE Department Seminar 

 

Towards High-Efficiency and High-Usability Hardware Acceleration 

 

Sitao Huang 

Ph.D. candidate 

Department of Electrical and Computer Engineering 

University of Illinois at Urbana-Champaign 

 

Friday, February 19, 2021 

10:00 am – 11:00 am 

Zoom Webinar Link: 

https://gmu.zoom.us/j/93154039697 

 

Abstract 

 

The exploding complexity and computation efficiency requirements of modern applications are stimulating a strong demand for hardware acceleration with heterogeneous platforms such as FPGAs. The stringent requirements of these modern application also pose several challenges for hardware acceleration systems. In particular, achieving high-efficiency, high-usability hardware acceleration targeting highly heterogeneous systems is one of the major challenges. In this talk, I will first give an overview of the challenges that modern hardware acceleration systems are facing, as well as my previous works in tackling these challenges. I will then introduce my recent representative works in detail, including PyLog language and compiler for Python-based high-level programming for FPGAs, Tangram language and compiler for highly efficient GPU code generation, Chai-FPGA for enabling CPU-FPGA collaborative computing, etc. Evaluation shows the promising performance and flexibility of these works when solving the hardware acceleration challenges. I will conclude my talk with my envision of future hardware acceleration research.  

 

Bio 

 

Sitao Huang is a final year Ph.D. candidate at the Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, under the supervision of Prof. Deming Chen and Prof. Wen-mei Hwu. He received his B.Eng. degree in Electronics Engineering at Tsinghua University in 2014, and his M.S. degree in Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign in 2017. Sitao’s research interest includes highly efficient hardware acceleration, programming language and synthesis flow for hardware systems, and optimization of heterogenous systems. He is a recipient of 2019 Sundaram Seshu International Student Fellowship and 2018 Rambus Computer Engineering Fellowship. His research won several awards, including the Best Paper Nomination at ASP-DAC 2021, the Student Innovation Award at the 2018 IEEE HPEC Graph Challenge, and the first place at DAC 2019 System Design Contest.  



Patricia Sahs

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Department of Electrical and Computer Engineering

George Mason University

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